1. Field of the Invention
The present invention relates to an active matrix substrate for use in an active matrix type liquid crystal display using a thin film transistor (which will be abbreviated to TFT hereinafter) and to a manufacturing method thereof. More particularly, the present invention relates to reduction in production steps of a method for manufacturing an active matrix substrate.
2. Description of the Prior Art
An active matrix liquid crystal display using TFTs has an active matrix substrate on which pixel electrodes and TFTs for controlling a voltage applied to the pixel electrodes are arranged in the form of a matrix. The active matrix liquid crystal display has a structure that a liquid crystal is sandwiched between the active matrix substrate and an opposed substrate and the liquid crystal is driven by a voltage applied between the pixel electrode and the other electrode. In this case, there is a liquid crystal display adopting a vertical electric field system, in which the pixel electrode on the active matrix substrate is constituted by a transparent electrode and a voltage is applied between the pixel electrode and a transparent common electrode formed on the opposed substrate as the other electrode in order to drive the liquid crystal. Alternatively, there is a liquid crystal display adopting a horizontal electric field system, in which the pixel electrode on the active matrix substrate and the common electrode are constituted by a pair of comb-like electrodes and a voltage is applied between these electrodes to drive the liquid crystal. At any rate, the TFT and the pixel electrode must be finely formed on the active matrix substrate, and nowadays the TFT and the pixel electrode are formed by a photolithography technique.
FIG. 1 is a cross-sectional view showing a one-pixel area of a TFT and a pixel electrode having the prior art structure provided on an active matrix substrate. Here, a technique disclosed in Japanese Patent Application Laid-open No. 268353/1998 is illustrated. In manufacture of the TFT and the pixel electrode, the first metal thin film is formed on a transparent insulating substrate 300. In the first photolithography step (which will be abbreviated to a PR step hereinafter) using photoresist, the first metal thin film is patterned to form a gate electrode 301 and a gate bus line 302 connected to this gate electrode 301. Subsequently, the first insulating film 303 as a gate insulating film, an intrinsic amorphous silicon film (which will be referred to as an intrinsic a-Si film hereinafter) 304, and an ohmic contact film 305 consisting of the a-Si film in which impurities are introduced are sequentially superimposed on the insulating substrate 300.
The ohmic contact film 305 and the intrinsic a-Si film 304 are then patterned in the second PR step. Further, the second metal thin film is deposited, and the second metal thin film is patterned by the third PR step to form a drain electrode 306 connected to a drain bus line, and a source electrode 307.
Then, the second insulating film 308 is deposited on the entire surface. Further, by the fourth PR step, a pixel contact hole 309 and a drain bus line contact hole (not shown) which pierce the second insulating film 308 and reaches the surface of the source electrode 307 and the drain bus line respectively are opened through the second insulating film 308. Furthermore, a gate bus line contact hole (not shown) which reaches even to the surface of the gate bus line is opened through the first insulating film 303 and the second insulating film 308. Moreover, a transparent electrode film, e.g., an ITO (INDIUM TIN OXIDE) film is deposited on the entire surface, and the transparent electrode film is patterned by the fifth PR step to form a pixel electrode 310 connected to the source electrode 307. In addition, although not illustrated in FIG. 1, a gate terminal portion connected to the gate bus line and a drain terminal portion connected to the drain bus line are simultaneously formed.
Such a prior art active matrix substrate requires five PR steps for forming the TFT, the pixel electrode, the gate terminal portion and the drain terminal portion. The five PR steps currently obstruct manufacturing the active matrix substrate at a low price, which is led by eliminating the cost required for the manufacturing steps. Thus, reduction in number of manufacturing steps, especially reduction in number of PR steps is examined. For example, Japanese Patent Application Laid-open No. 218925/1983 proposes a technique for reducing the PR steps to four steps by forming the pixel electrode, the gate electrode and the gate bus line by one PR step. Alternatively, a monthly publication FPD INTELLIGENCE 1999, pp. 31 to 35 or Japanese Patent Application Laid-open No. 2000-66240 discloses a technique for realizing patterning of films in different layers by one PR step by utilizing a half-tone exposure method to thereby reduce a number of the PR steps for the active matrix substrate.
In these improved techniques, the former technique has a process restriction that the gate electrode and the pixel electrode are formed by the same PR step and a structural restriction that the gate electrode and the pixel electrode are formed in the same layer. In particular, the structural restriction that the pixel electrode is formed in a lower layer must largely change the structure of the existing active matrix substrate. Additionally, in this structure, since the side surface of the intrinsic a-Si layer is not covered with a channel protection film but exposed, a liquid crystal layer exists through only a porous film such as a polyimide alignment layer when the liquid crystal display is configured. Further, there occurs a problem that impurities existing in the liquid crystal layer enter the intrinsic a-Si film by diffusion or an electric field to greatly deteriorate the characteristic of the TFT. In this regard, the latter technique has less structural and process restrictions and is particularly advantageous in that the pixel electrode can be manufactured as a layer structure similar to that of the existing active matrix substrate.
According to the latter technique utilizing the half-tone exposure method, as shown in schematic views illustrating a TFT portion of FIG. 2, a gate electrode 401 is first formed on an insulating substrate 400 and a gate insulating film 402, a intrinsic a-Si film 403, an ohmic a-Si film 404, and a metal film 405 are then sequentially superimposed thereon as shown in FIG. 2(a). Subsequently, a photoresist film 406 is coated thereon, and then exposed and developed to form a required pattern. At this time, a film thickness of the developed photoresist 406 becomes thinner in an area exposed by half-tone exposure, a part corresponding to a channel area of the TFT, than in a non-exposed area. Then, as shown in FIG. 2(b), the photoresist 406 is used as an etching mask to pattern the metal film 405, the ohmic a-Si film 404 and the intrinsic a-Si film 403 to form each island of the metal film 405, the ohmic a-Si film 404 and the intrinsic a-Si film 403. Thereafter, as shown in FIG. 2(c), when O2 gas is used to perform ashing of the photoresist 406, the photoresist in the area subjected to half-tone exposure is removed and the metal film 405 is exposed in this area. Furthermore, as shown in FIG. 2(d), the metal film 405 is etched by using the photoresist 406 subjected to ashing to be formed as a source electrode and a drain electrode. Subsequently, the ohmic a-Si film 404 is etched to form a channel area. Then, by removing the photoresist 406, the TFT is completed as shown in FIG. 2(e).
As described above, according to the technique disclosed in the latter reference, among the manufacturing steps explained with reference to FIG. 1, the second PR step and the third PR step can be combined as one PR step in the manufacturing process. As a result, by using half-tone exposure, the active matrix substrate having the structure similar to the prior art structure can be manufactured by the four PR steps.
In this manner, although the five PR steps can be reduced to the four PR steps in the conventional manufacturing method, it is difficult to further reduce a number of the PR steps. Therefore, it is desired to further decrease a number of manufacturing steps of the active matrix substrate to reduce the cost.
It is an object of the present invention to solve the above-described drawbacks and provide an active matrix substrate for a liquid crystal display and a manufacturing method thereof which realize reduction in a number of manufacturing steps to three PR steps and also realize reduction in cost.
That is, the active matrix substrate according to the present invention has the following structure.
There is provided an active matrix substrate for a liquid crystal display, having a plurality of gate wirings and drain wirings orthogonal to each other formed on a transparent insulating substrate and a thin film transistor and a pixel electrode formed in an area surrounded by the gate wirings and the drain wirings, wherein the gate wiring on the active matrix substrate has a structure that a protection film covers a metal wiring, the thin film transistor is composed of a gate electrode formed of a metal wiring, a gate insulating film, a semiconductor film and a protection film in the mentioned order from the bottom, and the gate insulating film and the semiconductor film are formed into a plane shape equal to or smaller than the gate electrode.
The gate wiring of the active matrix substrate and the gate electrode, the gate insulating film and the semiconductor film of the thin film transistor are formed by patterning a laminated film that is obtained by sequentially depositing a metal film, a gate insulating film and the semiconductor film on the transparent insulating substrate. A resist mask is formed on the laminated film, the resist mask consisting of a thick resist portion having a large film thickness and a thin resist portion thinner than the thick resist portion. The laminated film is etched by using the resist mask as an etching mask to form a laminated film pattern consisting of the metal film, the gate insulating film and the semiconductor film in each of a gate wiring area and a thin film transistor area. The thin resist portion in the resist mask on the laminated film pattern is removed to expose the laminated film pattern under the thin resist portion. After removing the thin resist portion, the exposed laminated film pattern is etched by using the remaining thick resist portion as an etching mask. Only the metal film remains in the gate wiring area, and the laminated film consisting of the metal film, the gate insulating film and the semiconductor film remains in the thin film transistor area, thereby forming the active matrix substrate.
Further, according to the present invention, there is provided a method for manufacturing an active matrix substrate, comprising the steps of: forming a resist mask having a thin portion and a thick portion on a laminated film consisting of a plurality of films; patterning the laminated film by using the resist mask as a mask; removing the thin portion of the resist mask to expose the laminated film in the removed portion; etching the exposed laminated film by using remaining portion in the thick portion of the resist mask as a mask; and etching an upper layer film of the laminated film to leave a lower layer film.
Specifically, the method adopts the basic structure comprising: a step of forming the first laminated film having a plurality of films laminated on a transparent insulating substrate; a step of forming the first resist mask consisting of the first thick resist portion with a large film thickness and the first thin resist portion having a smaller film thickness than the first thick resist portion on the first laminated film; a step of etching the first laminated film by using the first resist mask as a mask to form the first pattern consisting of the first laminated film; a step of etching the first resist mask to remove the first thin resist portion so that the first thick resist portion remains as the first remaining resist mask on the first pattern, and exposing a part of the first pattern; and a step of etching an exposed portion of the first pattern by using the first remaining resist mask as a mask to remove at least an uppermost layer film constituting the first pattern so that the second pattern consisting of films of the first laminated film excluding the upper most layer film is formed.